1. Field of the Invention
The present invention provides a power supply clamp circuit, and more particularity a power supply clamp circuit capable of providing an ideal bias control mechanism.
2. Description of the Prior Art
Integrated circuits, with advantages of smaller volume and higher density, are very applicable in complicated and concentrated modern microprocessor and memory circuits. Moreover, integrated circuits produced by semiconductor processes have already become mainstream in the design and manufacture of current large-scale circuits. In contrast with conventional scattered circuits, integrated circuits have a very serious problem of an exterior electrostatic discharge that easily damages fragile interior circuits. Because the size of each component and the distance between each component in integrated circuits shrink substantially, a larger pulse generated by an electrostatic discharge increases the possibility of damage to the components. Therefore, an electrostatic discharge damaging the components of integrated circuits becomes a more serious problem as smaller sizes of components are produced by advantaged process technologies.
Usually an electrostatic discharge occurs when an electrostatic carrier (such as a finger carrying charges) storing a huge amount of charges touches the integrated circuits. Therefore, usually there are two paths for charges of a carrier getting into the integrated circuits. One is from a signal end to get into the integrated circuits as a Pin-to-Pin Route, and the other is from a power supply end to get into the integrated circuits as Power-to-Ground Route. In the prior art, an electrostatic discharge level is generally defined as the level of electrostatic discharge that the integrated circuits are capable of tolerating while avoiding damage to the components. In order to enhance the electrostatic discharge level, the prior art usually sets up a clamp circuit between ends of a possible route for electrostatic discharge.
Please refer to FIG. 1. FIG. 1 is a perspective view of a prior art power supply clamp circuit 10 electrically connected to a first power supply source P1 and to ground. The power supply clamp circuit 10 comprises a first PMOS transistor 12, a first NMOS transistor 14, a second NMOS transistor 16, a resistor 18, and a capacitor 20. The first PMOS transistor 12 has a source electrically connected to a first voltage source P1, a gate electrically connected to a first node N1, and a drain electrically connected to a second node N2. The first NMOS transistor 14 has a drain electrically connected to the second node N2, a gate electrically connected to the first node N1, and a source connected to ground. The second NMOS transistor 16 has a drain electrically connected to the first voltage source P1, a gate electrically connected to the second node N2, and a source connected to ground. One end of the resistor 18 is electrically connected to the first voltage source P1 and another end of the resistor 18 is electrically connected to the first node N1. One end of the capacitor 20 is electrically connected to the first node N1 and another end of the capacitor 20 is connected to ground.
In FIG. 1, a combination of the resistor 18 and the capacitor 20 can be functionally regarded as a voltage generator to generate a voltage at the first node N1. The voltage at the first node N1 is a sensitive value to an electrostatic discharge and responds differently under a condition of normal operation and a condition of an electrostatic discharge in the integrated circuits. The electrostatic discharge phenomenon is a huge amount of charges performing a discharge to the first voltage source P1 that results in a voltage pulse increasing in velocity very quickly at the first voltage source P1.
Specifically, when the first voltage source P1 turns on during normal operation, a voltage at the first voltage source P1 increases in velocity very slowly such as from 0V to a predetermined operating voltage in few microseconds or even few milliseconds. However, when an electrostatic discharge occurs, a voltage pulse is generated and results in the first voltage source P1 increasing from in only few nanoseconds. Therefore, the voltage generator combined by the above-mentioned resistor 18 and capacitor 20 generates a voltage corresponding to different increasing velocities of the voltage at the first voltage source P1.
Those skilled in the art will recognize that the resistor 18 and the capacitor 20 function as a low-pass filter. When the first voltage source P1 turns on during normal operation, the voltage at the first voltage source P1 increases in velocity very slowly. Then, the voltage at the first node N1 and the voltage at the first voltage source P1 increases simultaneously. When an electrostatic discharge occurs, the voltage at the first voltage source P1 increases in velocity very quickly. At this time, because of how the low-pass filter works, during a transient time of the voltage at the first voltage source P1 starting to increase, the voltage at the first node N1 cannot completely respond with the voltage increasing velocity at the first voltage source P1. This results in an obvious voltage difference between the first voltage source P1 and the first node N1.
Because of the voltage generator formed by combining by the resistor 18 and the capacitor 20 has the above-mentioned characteristics, the first voltage source P1 turns on during normal operation. Then, a voltage difference between the first node N1 and the first voltage source P1 will not appear during a voltage increasing process at the first voltage source P1. That is, a voltage difference Vspp1 between a source (as the voltage source P1) and a gate (as the first node N1) of the first PMOS transistor 12 is equal to 0 V. Then, the PMOS transistor 12 turns off during the voltage increasing process at the first voltage source P1. After a voltage at the first node N1 increases to a voltage that can turn on the first NMOS transistor 14, a voltage at the second node N2 descends to ground when the first NMOS transistor 14 turns on. Therefore, the second NMOS transistor 16 always keeps the status of turning off to avoid the leakage current from the first voltage source P1 to ground.
A voltage pulse is generated at the first voltage source P1 in very quick velocity when an electrostatic discharge occurs. Then, as mentioned above a voltage difference is generated between the first node N1 and the first voltage source P1 by means of the function of low-pass filter. That is, a voltage difference Vsgp12 between a source (as the first voltage source P1) and a gate (as the first node N1) of the first PMOS transistor 12 is greater than a threshold voltage of the PMOS transistor 12 to result in the first PMOS transistor 12 getting into the status of turning on. When the first PMOS transistor 12 turns on, a voltage at the second node N2 will be pulled up by the first voltage source P1 to make the second NMOS transistor 16 turn on. Through the above-mentioned actions, the power supply clamp circuit 10 provides a current path from the first voltage source P1 to ground by means of turning on the second NMOS transistor 16. When the voltage of the first voltage source P1 achieves the device''s breakdown voltage, the ESD current is bypassed through the parasitic. Therefore, a voltage pulse at the first voltage source P1 generated by an electrostatic discharge performs a discharge through the path to ground and does not to damage the interior circuits of integrated circuits. Please note that the second NMOS transistor 16 usually is designed as a bigger size of transistor to enhance an electrostatic discharge level of the power supply clamp circuit 10.
However, the electrostatic discharge level of the power supply clamp circuit 10 highly relates with a gate bias of the second NMOS transistor 16 as a gate bias effect. When the PMOS transistor 12 turns on to make the second NMOS transistor 16 turn on, a bias at the gate (as the second node N2) of the second NMOS transistor 16 must be controlled in a suitable voltage range capable of maintaining the best status of an electrostatic discharge level of the power supply clamp circuit 10. When a bias at the gate of the second NMOS transistor 16 is higher, the electrostatic discharge level of the power supply clamp circuit 10 will decline substantially.
Therefore, in order to control the gate bias of the second NMOS transistor 16 within a suitable voltage range, a circuit designer must perform a very precise control of parameters such as the length and width of the gate of the first PMOS transistor 12 and the first NMOS transistor 14 during a designing process of the power supply clamp circuit 10. This increases time and human costs of a circuit design.